1. Field of the Invention
The present invention relates to electronic systems, and in particular to a system and method for providing power to a component such as a processor while providing an integrated approach to managing thermal dissipation and electromagnetic interference.
2. Description of the Related Art
In high-performance desktop or high-end workstation/servers, high-speed microprocessor packaging must be designed to provide increasingly small form-factors. Meeting end user performance requirements with minimal form-factors while increasing reliability and manufacturability presents significant challenges in the areas of power distribution, thermal management, and electromagnetic interference (EMD containment.
To increase reliability and reduce thermal dissipation requirements, newer generation processors are designed to operate with reduced voltage and higher current. Unfortunately, this creates a number of design problems.
First, the lowered operating voltage of the processor places greater demands on the power regulating circuitry and the conductive paths providing power to the processor. Typically, processors require supply voltage regulation to within 10% of nominal. In order to account for impedance variations in the path from the power supply to the processor itself, this places greater demands on the power regulating circuitry, which must then typically regulate power supply voltages to within 5% of nominal.
Lower operating voltages have also lead engineers away from centralized power supply designs to distributed power supply architectures in which power is bussed where required at high voltages and low current, where it is converted to the low-voltage, high-current power required by the processor by nearby power conditioning circuitry.
While it is possible to place power conditioning circuitry on the processor package itself, this design is difficult to implement because of the unmanageable physical size of the components in the power conditioning circuitry (e.g. capacitors and inductors), and because the addition of such components can have a deleterious effect on processor reliability. Such designs also place additional demands on the assembly and testing of the processor packages as well.
Further exacerbating the problem are the transient currents that result from varying demands on the processor itself. Processor computing demands vary widely over time, and higher clock speeds and power conservation techniques such as clock gating and sleep mode operation give rise to transient currents in the power supply. Such power fluctuations can require changes in hundreds of amps within a few nanoseconds. The resulting current surge between the processor and the power regulation circuitry can create unacceptable spikes in the power supply voltage       (                  e        .        g        .                                   ⁢        dv            =              IR        +                  L          ⁢                                           ⁢                                    ⅆ              i                                      ⅆ              t                                            )    .
FIG. 1 is a plot of a typical transient response 102 at the interface between the voltage regulator and the processor, and comparing that response with nominal 104 and minimum 106 supply voltages. Note that the transient interface voltage includes an initial spike which must not extend below an acceptable margin 108 above the minimum supply voltage, and a more sustained voltage droop 110. In order to retain the supply voltage within acceptable limits 104 and 106 and to reduce variations in supplied power to the processor, the power and ground planes, power and ground vias, and capacitor pads must be designed to ensure low inductance power delivery paths to the processor.
FIG. 2 is a diagram of an exemplary distributed power supply system 200. The power supply system 200 includes a motherboard 202 having a power supply unit 206 such as a DC/DC voltage regulator mounted thereon. The motherboard 202 has a plurality of signal traces, including a first signal trace having a high-voltage/low-current (HV/LC) power signal 204 (which could also be supplied by a wire, for example). The power supply unit 206 accepts the HV/LC power signal and via electrical circuitry including components 208, converts it to a conditioned high-current/low-voltage (HC/LV) signal 210 that is provided to a second signal trace in the motherboard 202.
A socket 214 is electrically coupled to the motherboard 202 via a first electrical connection 212, such as a ball grid array (BGA). The socket 214 includes internal electrical connections for providing the HC/LV signal to pins 216 electrically coupled between the socket 214 and a power regulation module 218. Similarly, the power regulation module 218 is electrically coupled to a substrate 222 via a second electrical coupling 220 such as a BGA. The processor (e.g. the die) 226 is electrically coupled to the substrate 222 via a third electrical coupling 224. The HC/LV signal is provided to the processor via the circuit path described above. As described earlier distributed power systems such as is illustrated in FIG. 1 still result in unacceptable impedances that cause voltage drops in the power distribution path.
In order to obtain the proper margin as shown in FIG. 1, surge currents are managed by placing decoupling capacitors 228 and other components throughout the power delivery subsystem, including on the power regulation module 218, on the motherboard, on the processor die package, and on the die itself. This not only increases costs, but consumer critical silicon area, chip package and board real estate. Further, for microprocessors operating at more than 200 MHz, the only serviceable capacitor is an on-die capacitor, or one that is very close to the die. On-die capacitors are common in PC-class processors.
The need for higher performance and increased functional integration in smaller processor dies has also lead to higher heat-flux concentrations in certain areas of the processor die. In some cases, the resulting surface energy densities approach unmanageable levels. Processor reliability is exponentially dependent on the operating temperature of the die junction. Lowering temperatures in the order of 10-15 degrees centigrade can double the processor lifespan. Thermal management issues now present some of the largest obstacles to further processor miniaturization and increases in processor speed.
Thermal management must also take nearby voltage regulator efficiencies into account. An 85% efficient voltage regulator driving a 130 watt device dissipates over 20 watts. This makes it more difficult to locate the voltage regulator close to the CPU because the thermal management structures for each component conflict. Electromagnetic interference (EMI) is also a problem. In a typical computer system, the processor 226 is by far the largest source of electromagnetic energy. Containing radiated and conducted emissions at the source (at the processor package) would make the system design easier for computer OEMs. Because of the generation of higher order harmonics, Federal Communications Commission (FCC) regulations require emission testing at frequencies up to five times the processor clock frequency or 40 GHz, whichever is lower.
The primary component of EMI is a radiated electromagnetic wave which gets smaller as frequencies increase. EMI management, which generally is performed on the chassis level rather than the component level, is typically accomplished by reducing the size of openings in the system, effectively blocking the electromagnetic waves. However, using smaller apertures introduces thermal management problems because of decreased airflow.
Another method for reducing EMI is to ground any heat sinks. Noise coupled from the processor package to the heat sink may cause the heat sink to act as an antenna and re-radiate the noise. However, it is typically not possible to ground the heatsink through the processor package. Also, while the grounding of the heatsink may reduce EMI, this technique is typically insufficient to meet EMI requirements, and additional shielding is typically necessary.
What is needed is an integrated processor packaging technology that provides the required form factor while providing high current low voltage to the processor without requiring bulky external capacitors to account of path inductances, and while managing thermal and EMI emissions within satisfactory levels. The present invention satisfies that need.